1. Field of the Invention
The present invention relates to an apparatus for performing logic simulation of a semiconductor device.
2. Description of the Related Art
A semiconductor device generally includes a logic circuit constructed by a large number of logic elements. For example, when a new semiconductor device is to be designed, logic elements are logic-simulated by a logic simulator to check whether a designed logic circuit operates as expected. Such a logic simulator is conventionally arranged by software by using a versatile computer or the like.
In order to increase an operation speed in logic simulation performed by a logic simulator, Published Unexamined Japanese Patent Application No. 59-3652 or 63-257841 proposes a logic simulator in which a portion of software of the logic simulator as described above is replaced by hardware.
Conventionally, when the level of the signal input to a gate (cell) constructing a logic circuit varies, that is, an event is generated, the event is output from the gate with a delay time according to rising or falling characteristic of the cell when another event is generated within the delay time from the input time to the output time, the output has an "X" state (undefined state). In addition, a phenomenon called "passing" in which an order of an output event and an order of an input event are reversed may occur. Also, the timing errors such as set-up time, wheel time and the like may occur in a memory cell such as flip-flop, counter and the like.
Thus, the conventional logic simulator is designed to select one of two modes. In one mode, a delay time is not calculated and simulation is executed without a timing error being detected. In the other mode, the 10 delay time is calculated, simulation is executed while simultaneously detecting the occurrence of a timing error, and a timing error, if it occurs, is displayed.
with the above conventional logic simulator, it is possible to know whether or not a timing error occurs, by looking at a display screen. However, since the occurrence of the timing error is not reflected in the results of simulation, what is simulated differs from an actual state.